Sr. ASIC Verification Engineer

Scottsdale, AZ

Posted: 07/19/2019 Employment Type: Contract Industry: Engineering Job Number: 229700

The successful candidate must have the following experience:

Eight to ten years of experience leading/managing verification of FPGA/ASICSs

Development of verification matrix to ensure coverage of requirements

Defining regression test suits

Managing regression simulations

Tracking and resolving design bugs

Eight to ten years of experience using System Verilog for verification

Developing and applying System Verilog Assertions (SVA) within an assertion-based verification strategy

Developing functional coverage (covergroups, cover points) to measure test effectiveness

Developing random constraints to guide constrained random simulations

Experienced with Direct Programming Interface (DPI)

Five or more years of experience with Open Verification Methodology (OVM, Universal Verification Methodology (UVM) or Verification Methodology Manual (VMM).   UVM is preferred.

Experienced with developing testbench infrastructure (agents, drivers, monitors, interfaces, scoreboards, environments, etc.)

Thoroughly familiar with communication between static (module-based) and dynamic (class-based) components within a test environment

Experienced with test/stimulus development using transactions, sequences and sequencers

Key Words:  SystemVerilog, SystemVerilog Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random
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